The present invention relates to a method for manufacturing a semiconductor device; and, more particularly, to a method for manufacturing a magnetic random access memory (RAM) having characteristics of a non-volatile memory such as a flash memory, a faster speed than a static RAM and integration identical to that of a dynamic RAM.
Most of semiconductor memory manufacturing companies are developing a magnetic RAM using ferromagnetic materials as one of the next generation memory devices.
The magnetic RAM is a memory device that is manufactured by forming a multi-layer of ferromagnetic thin films and reads and writes information by detecting a current variation according to the magnetization direction of each thin film. Therefore, the magnetic RAM can accomplish high speed, low power and high integration by using unique characteristics of a magnetic film, and perform the operation of a non-volatile memory, e.g., a flash memory.
The magnetic RAM employs a method for implementing a memory device by utilizing the spin polarization magnetic permeation phenomenon or the giant magnetoresistance (GMR) effect caused by the spin having a substantial influence on the propagation phenomenon of an electron.
The magnetic RAM implements a GMR magnetic memory device by using a phenomenon in which there is a big difference between the resistance when the spin directions of two magnetic layers are identical to each other, the two magnetic layers including a non-magnetic layer therebetween, and the resistance when the spin directions of the two magnetic layers are different from each other.
The magnetic RAM using the spin polarization magnetic permeation phenomenon embodies a magnetic permeation junction memory by utilizing a phenomenon in which the current permeation well occurs in the case in which the spin directions of two magnetic layers are identical to each other, the two magnetic layers including a dielectric layer therebetween, compared to the case in which the spin directions of the two magnetic layers are different from each other.
However, research on the magnetic RAM is in the early stage and is mainly concentrated on the formation of a multi-layer of magnetic thin films. Therefore, research on a unit cell structure and peripheral detecting circuits is deficient.
Referring to FIG. 1, there is shown a cross-sectional view of a conventional magnetic RAM device.
A gate electrode 33, i.e., a first word line, is formed on the top of a semiconductor substrate 31.
Then, source/drain junction regions 35a and 35b are formed inside the semiconductor substrate 31 on both sides of the first word line 33 and there are formed a ground line 37a and a first conductive layer 37b connected to the source/drain junction regions 35a and 35b, respectively. At this time, the ground line 37a is generated in the process of making the first conductive layer 37b. 
Subsequently, there are formed a first layer insulating film 39 for planarization of the top surface of an intermediate product and a first contact plug 41 exposing the first conductive layer 37b. 
There is patternized a lower lead layer 43 which is a second conductive layer and connected to the first contact plug 41.
A second layer insulating film 45 is formed to planarize the top surface of the intermediate product and, then, there is formed a second word line W/L2 being used as a write line 47 on the top of the second layer insulating film 45.
To planarize the top surface of the intermediate product including the write line 47, a third layer insulating film 48 is constructed thereafter.
A second contact plug 49 is formed to expose the second conductive layer 43.
Then, there is formed a seed layer 51 attached to the second contact plug 49. At this time, the seed layer 51 is made covering an upper portion of the second contact plug 49 and that of the write line 47.
Subsequently, a magnetic tunnel junction (MTJ) cell 100 is formed by sequentially stacking an antiferromagnetic layer (not shown), a pinned ferromagnetic layer 55, a tunnel junction layer 57 and a free ferromagnetic layer 59. The MTJ cell 100 has a pattern size identical to that of the write line 47 and is aligned with the write line 47.
Herein, the antiferromagnetic layer plays a role of keeping the magnetization direction of the pinned ferromagnetic layer unchanged, so that the magnetization direction of the tunnel junction layer 57 is fixed in one direction. Meanwhile, the free ferromagnetic layer 59 can store xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d information according to its magnetization direction when its magnetization direction is changed by an external magnetic field.
Finally, after forming a fourth layer insulating film 60 to planarize the top surface of the intermediate product and expose the free ferromagnetic layer 59, a bit line 61 is formed thereon.
Referring to FIG. 2, there is illustrated an enlarged cross-sectional view of a portion A in FIG. 1.
As shown in FIG. 2, the second word line W/L247 and the seed layer 51 maintain a distance xe2x80x9cdxe2x80x9d therebetween and the MTJ cell 100 is formed by stacking the pinned ferromagnetic layer 55, the tunnel junction layer 57 and the free ferromagnetic layer 59 on the top of the seed layer 51.
Herein, the distance xe2x80x9cdxe2x80x9d is made of the third layer insulating film 48 and has a size of about 1000 to about 2000 xc3x85.
As described above, the conventional semiconductor device manufacturing method has a problem of requiring a lot of current to perform a writing operation since the distance between the seed layer and the second word line under the MTJ cell is too long.
It is, therefore, a primary object of the present invention to provide a method for manufacturing a semiconductor device capable of performing a writing operation with a small amount of current by forming a thin oxide film on the surface a second word line being used as a write line so as to reduce the distance between an MTJ cell and the second word line.
In accordance with the present invention, there is provided a method for manufacturing a semiconductor device, comprising the steps of:
(a) forming a word line on a semiconductor substrate, wherein the word line is used as a write line;
(b) forming a planarized layer insulating film exposing the surface of the word line;
(c) forming a dielectric film on the surface of the word line;
(d) forming a seed layer connected to the word line through the dielectric film; and
(e) configuring a cell on the top of the seed layer and in an upper portion of the word line.